1. Field of the Invention
This invention relates to computer systems and, more particularly, to shared input/output (I/O) resources
2. Description of the Related Art
There have been significant increases in the effective throughput of a variety of I/O devices used in computing systems. In the recent past, a number of new communication standards have been introduced. For example, 10 Gigabit Ethernet may allow up to ten gigabits of information to be conveyed and Peripheral Component Interconnect Express (PCIe™) Generation 1 may allow up to 2.5 Gbits per lane. In many computer systems, a single processor or processing module typically does not use that much I/O bandwidth. Accordingly, in an effort to increase hardware resource utilization, sharing of I/O hardware resources may be desirable.
One mechanism for sharing resources that use PCIe interfaces is to virtualize the resources across multiple processing elements. Thus, I/O virtualization standards have been introduced, such as for example, the single root and multi-root PCIe specifications. However, there are issues with sharing hardware resources. For example, many high-speed serial link technologies use a layered communication protocol. In such technologies, it may be challenging to process transactions that may be issued to a shared I/O subsystem by multiple processors or processing units, each of which may be running multiple processes.